Fast high resolution analog-to-digital (A/D) converters are most often realized utilizing successive approximation techniques in which a successive approximation register is clocked so as to provide an increasing or decreasing series of binary numbers representing predetermined weights. Signals representing these numbers are coupled to the switching elements of a digital-to-analog converter (DAC) which converts the numbers into analog voltages or currents against which an analog input signal is compared. The magnitude of the analog input signal is compared with the weightings provided by the DAC starting with the most significant bit (MSB) to ascertain whether the analog signal is above or below the level established by the bit. If above, the state of the corresponding binary element of the successive approximation register is not changed. If below, the state of the binary element is reversed. After cycling through, for instance, 12 bits representing weightings of 2048, 1024, 512, 256, 128, 64, 32, 16, 8, 4 and 2, 1 the sum equalling 4095, the cycling is inhibited and the state of the successive approximation register is read out as the digital approximation of the analog signal. Thus, for instance, for an amplitude of 30, the final state of the register would be 000000011111=31.
To achieve the required accuracy, speed and stability, high performance linear and digital circuitry is needed. The discipline surrounding linear circuits and digital techniques often dictate that a hybrid approach to the construction of an analog-to-digital converter will yield the best, most economical performance. In the past, most of successive approximation analog-to-digital converters have worked in the voltage domain in which so-called "R, 2R" resistor ladders are utilized to produce binary weighted voltages in accordance with the output state of the successive approximation register. In general, digital-to-analog converters utilizing R, 2R ladders have also utilized bipolar switching circuits so as to switch in resistors corresponding to the digital input code from the successive approximation register. Bipolar switching circuitry is utilized because it is relatively fast, the speed of the bipolar switching circuitry being basically a function of the relatively low output capacitances involved. Conventional comparator circuits operating in the voltage domain are compatible with the bipolar circuits and, in general, are compatible with the speed associated with bipolar switching arrangements.
There are, however, problems associated with the aforementioned conventional successive approximation analog-to-digital converter which center around the high current drain associated with bipolar switching. Moreover, R, 2R ladders have linearity characteristics which are highly sensitive to the accuracy of the resistor values. When R, 2R ladders are utilized, the accuracy of the conversion is much more sensitive to the individual resistor values than is an equal current digital-to-analog converter in which a resistor network is provided to generate equal currents. These currents when summed, provide for current steps which increase with increases in the binary number provided by the successive approximation register. Not only are there linearity problems associated with the R, 2R networks, but also switching errors greatly affect the d.c. stability of the output from such a digital-to-analog converter.
In addition to problems with linearity, the aforementioned current drain is excessive when utilizing bipolar switching elements. In an effort to decrease the power consumption of such a circuit, complementary metal oxide semiconductor (C-MOS) devices may be utilized in the switching circuits for the digital-to-analog converter. However C-MOS switching circuits, while providing order of magnitude advantage in decreased power consumption, have high output capacitances. High output capacitance severely limits the speed with which the analog-to-digital conversion can proceed, and thus the benefits of C-MOS technology have not been available for use in analog-to-digital conversion. Moreover, the inability to utilize C-MOS technology due to speed requirements has, in general, prohibited the advantages of lower switching errors and higher signal-to-noise ratios associated with C-MOS switching circuits when utilized in combination with equal current digital-to-analog converters.
Another reason C-MOS circuitry has not been utilized for analog-to-digital converters has been the problem of low gain for the required current comparator circuitry. Gain problems associated with current comparators generally center around the current-to-voltage converter utilized ahead of a conventional voltage comparator, with the gain of the current-to-voltage converter stage in general causing attenuation. The reason that the gain through the conventional current-to-voltage converter is generally less than one, is a result of the high quiescent bias current necessary to maintain the conducting state of the transistors utilized in the converter when the converter is subjected to overcurrents. High quiescent bias necessitates the utilization of relatively low-valued load resistors which in turn reduces the gain of the comparator.
Moreover, with respect to d.c. stability, since all digital-to-analog converters require highly stable reference supplies, it is often only with difficulty that tight tolerances can be maintained through the utilization of conventional reference supplies having conventional inverters.
Finally, inexpensive yet accurate clocking systems which are at the same time low-power, have not been available for the clocking and control of analog-to-digital converters. With the exception of crystal controlled clocks which are prohibitively expensive, most C-MOS clocking circuits have clock frequencies which are highly dependent on variations in device thresholds.
As a result, high accuracy, high linearity, stable, low power successive approximation monolithic analog-to-digital converters have not previously been available.